1. Field of the Invention
The present invention relates to a method and a driving circuit for driving a liquid crystal display (LCD), and portable electronic devices employing the driving circuit and more particularly to the method and the driving circuit for driving the LCD used as a display section having a comparatively small display screen of portable electronic devices such as a notebook computer, palm-size computer, pocket computer, personal digital assistance (PDA), portable cellular phone, personal handy-phone system (PHS) or a like and to the portable electronic devices equipped with such the driving circuit for the LCD.
The present application claims priority of Japanese Patent Application No. 2001-008322 filed on Jan. 16, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 20 is a schematic block diagram for showing configurations of a driving circuit for a conventional color LCD 1. The conventional color LCD 1 is an active-matrix driving type color LCD in which, for example, a thin film transistor (TFT) is used as a switching element. In the color LCD 1 of the example, a region surrounded by a plurality of scanning electrodes (gate lines) placed at established intervals in a row direction and by a plurality of data electrodes (source lines) placed at established intervals in a column direction, is used as a pixel. Each pixel of the color LCD 1 has a liquid crystal cell serving as an equivalent capacitive load, common electrode, TFT used to drive the corresponding liquid crystal cell, and capacitor used to accumulate a data electrode for one vertical sync period. To drive the color LCD 1 of the example, a data red signal, data green signal, and data blue signal produced based respectively on a red data DR, green data DG, and blue data DB contained in digital video data are fed to the data electrode while scanning signals produced based on a horizontal sync signal SH and a vertical sync signal SV are fed to a scanning electrode, with a common potential Vcom being applied to the common electrode. This enables a color character, image, or a like to be displayed on a display screen of the color LCD 1 of the example. Moreover, the color LCD 1 of the example is a so-called “normally white mode” type LCD which provides a high transmittance while a voltage is not being applied.
Moreover, the driving circuit to drive the above color LCD 1 chiefly includes a control circuit 2, a gray scale power source 3, a common power source 4, a data electrode driving circuit 5, and a scanning electrode driving circuit 6. The control circuit 2 is made up of, for example, an application specific integrated circuit (ASIC) adapted to convert 6 bits of the red data DR, 6 bits of the green data DG, and 6 bits of blue data DB, all of which are fed from an outside, into 18 bits of display data D00 to D05, D10 to D15, D20 to D25 and to feed them to the data electrode driving circuit 5. Moreover, the control circuit 2 produces a strobe signal STB, clock CLK, horizontal start pulse STH, polarity signal POL, vertical start pulse STV, and data inverting signal INV, based on a dot clock DCLK, the horizontal sync signal SH, the vertical sync signal SV, or a like, all which are fed from the outside, and feeds them to the gray scale power source 3, common power source 4, data electrode driving circuit 5, and scanning electrode driving circuit 6. The strobe signal STB is a signal having a same period as that of the horizontal sync signal SH. The clock CLK has a same frequency as that of a dot clock DCLK or has a frequency being different from that of the dot clock DCLK and, as described later, is used to produce sampling pulses SP1 to SP176 using the horizontal start pulse STH in a shift register 12 making up a data electrode driving circuit 5. The horizontal start pulse STH has a same period as the horizontal sync signal SH and is a signal being delayed by several pulses of the clock CLK behind the strobe signal STB. Moreover, the polarity signal POL is a signal that inverts in every one horizontal sync period, that is, for every one line, to drive the color LCD 1 with alternating current. The polarity signal POL inverts in every one horizontal sync period. The vertical start pulse STV is a signal having a same period as that of the vertical sync signal SV. The data inverting signal INV is a signal used to reduce power consumption in the control circuit 2. When present display data D00 to D05, D10 to D15, and D20 to D25 each being made up of 18 bits are those resulting from inversion of previous display data D00 to D05, D10 to D15, and D20 to D25 each being made up of 18 bits, by 10 bits or more, instead of inverting the present display data D00 to D05, D10 to D15, and D20 to D25, the data inverting signal INV is inverted in synchronization with the clock CLK. The reason that the data inverting signal INV is used here will be described below. That is, in portable electronic devices equipped with the driving circuit for the above color LCD 1, usually, the control circuit 2, the gray scale power source 3, or a like are placed on a printed board, however, the data electrode driving circuit 5 is placed on a film carrier tape which connects the printed board electrically to the color LCD 1 and is packaged as a tape carrier package (TCP). The printed board is placed in an upper portion of a rear face of a backlight attached to a rear of the color LCD 1. Therefore, in order to feed the 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 from the control circuit 2 to the data electrode driving circuit 5, formation of 18 pieces of wirings on the film carrier tape on which the data electrode driving circuit 5 is placed is required. Each of the 18 pieces of the wirings has a wiring capacitor. Moreover, an inputting capacitor of the data electrode driving circuit 5 when viewed from the control circuit side 2 has a capacitance of about 20 pF. Therefore, if the 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 have to be inverted and to be fed from the control circuit 2 to the data electrode driving circuit 5, a current to be used for charging and discharging the above wiring capacitor and the inputting capacitor is required. To solve this problem, instead of inverting the 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 themselves, by inverting the data inverting signal INV, the charging and discharging current to be fed to the above wiring capacitor and inputting capacitor is reduced and power consumption of the control circuit 2 is reduced.
The gray scale power source 3, as shown in FIG. 21, includes resistors 71 to 710, switches 8a, 8b, 9a, and 9b, inverter 10, and voltage followers 111 to 119. The gray scale power source 3 amplifies gray scale voltages V11 to V19 which are set to make gamma correction and feeds the amplified gray scale voltages V11 to V19 to the data electrode driving circuit 5. A potential of each of the gray scale voltages V11 to V19 is inverted between positive polarity and negative polarity for one line, in response to a polarity signal POL, relative to a common potential Vcom being applied to a common electrode of the color LCD 1. Each of the resistors 71 to 710 has a different resistance value and the resistors 71 to 710 are cascade-connected to each other. To one terminal of the switch 8a is applied a supply voltage VDD and another terminal is connected to one terminal of the resistor 71. When the polarity signal POL is at a high level, the switch 8a is turned ON and feeds the supply voltage VDD to one terminal of the resistors 71 to 710 that are cascade-connected. One terminal of the switch 8b is connected to a ground and another terminal is connected to one terminal of the resistor 71. When an output signal of the inverter 10, that is, an inverted signal of the polarity signal POL is at a high level, the switch 8b is turned ON and causes one terminal of the resistors 71 to 710 being cascade-connected to be connected to the ground. One terminal of the switch 9a is connected to a ground and another terminal is connected to one terminal of the resistor 710. When the polarity signal POL is at a high level, the switch 9a is turned ON and causes another terminal of the resistors 71 to 710 being cascade-connected to be connected to the ground. To one terminal of the switch 9b is applied the supply voltage VDD and another terminal of the switch 9b is connected to one terminal of the resistor 710. When an inverted signal of the polarity signal POL is at a high level, the switch 9b is turned ON and causes the supply voltage VDD to be applied to another terminal of the resistors 71 to 710 being cascade-connected.
That is, the gray scale power source 3, while the polarity signal POL is at a high level, produces gray scale voltages V11 to V19 (GND<V19<V18<V17<V16<V15<V14<V13<V12<V11<VDD) each having positive polarity which have been obtained by dividing the supply voltage VDD based on a resistance ratio of the resistors 71 to 710 and, after having amplified these voltages by the voltage followers 111 to 119, feeds them to the data driving circuit 5. On the other hand, the gray scale power source 3, while the polarity signal POL is at a low level, produces gray scale voltages V11 to V19 (GND<V11<V12<V13<V14<V15<V16<V17<V18<V19<VDD) each having negative polarity which have been obtained by dividing the supply voltage VDD based on a resistance ratio of the resistors 71 to 710 and, after having amplified these voltages by the voltage followers 111 to 119, feeds them to the data driving circuit 5.
The common power source 4, while the polarity signal POL is at a high level, causes the common potential Vcom to be at a ground level and, while the polarity signal POL is at a low level, causes the common potential Vcom to be at a level of the supply voltage (VDD) and supplies these voltages to a common electrode of the color LCD 1. The data electrode driving circuit 5 selects a predetermined gray scale voltage with timing when the strobe signal STB, clock CLK, horizontal start pulse STH and data inverting signal INV are fed from the control circuit 2 and, by using the 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 which are also fed from the control circuit 2, selects a predetermined gray scale voltage and then applies them to a corresponding data electrode in the color LCD 1 as a data red signal, data green signal, and data blue signal. The scanning electrode driving circuit 6 produces scanning signals, sequentially, with timing when a vertical start pulse STV is supplied from the control circuit 2, and then applies them sequentially to a corresponding scanning electrode in the color LCD 1.
Next, the data electrode driving circuit 5 is explained in detail. In the example, let it be assumed that the color LCD 1 provides 176×220 pixel resolution. Since one pixel is made up of three dot pixels including red (R), green (G), and blue (B) colors, the total number of the dot pixels is 528×220 pixels.
The data electrode driving circuit 5 includes, as shown in FIG. 22, a shift register 12, data buffer 13, data register 14, control circuit 15, data latch 6, gray scale voltage generating circuit 17, gray scale voltage selecting circuit 18 and outputting circuit 19. The shift register 12 is a serial-in parallel-out type shift register 12 made up of 176 pieces of delay flip-flops (DFF) which performs shifting operations to shift the horizontal start pulse STH fed from the control circuit 2 in synchronization with the clock CLK fed from the control circuit 2 and also outputs 176 bits of parallel sampling pulses SP1 to SP176.
The data buffer 13, as described above, inverts 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 being fed from the control circuit 2, based on the data inverting signal INV used to reduce power consumption of the control circuit 2 and then feeds the inverted data to the data register 14 as display data D′00 to D′05, D′10 to D′15, and D′20 to D′25. Or the data buffer 13 feeds the above 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 being fed from the control circuit 2 without inverting them as the display data D′00 to D′05, D′10 to D′15, and D′20 to D′25. FIG. 23 is a schematic block diagram showing one example of configurations of part of a data buffer making up the driving circuit for the conventional color LCD 1. The data buffer 13 is made up of 18 pieces of data buffer sections 13a1 to 13a18 and one control section 13b. The control section 13b is made up of two groups of inverters each having a plurality of inverters being connected in series to each other. The control section 13b causes the data inverting signal INV and the clock CLK fed from the control circuit 2 to be delayed by predetermined period of time behind corresponding inverter groups and feeds them to the data buffer sections 13a1 to 13a18 as a data inverting signal INV1 and a clock CLK1. Configurations of each of the data buffer sections 13a1 to 13a18 are the same except that subscripts of components differ from each other and subscripts of signals input and output from and to the data buffer sections 13a1 to 13a18 differ from each other and therefore only the configurations of the buffer section 13a1 are described. The data buffer section 13a1, as shown in FIG. 23, includes a DFF 201, inverters 211, 221, and 231, and switching unit 241. The DFF 201, after having held one bit of the display data D00 during one pulse of the clock CLK1 in synchronization with the clock CLK1, outputs it. The inverter 211 inverts output data from the DFF 201. The switching unit 241 is made up of a switch 241, and 241b. In the switching unit 241, while the data inverting signal INV1 is at a high level, the switch 241a is turned ON and outputs data fed from the DFF 201 and, while the data inverting signal INV1 is at a low level, the switch 241b is turned ON and outputs data fed from the inverter 211. The inverter 221 inverts data fed from the switching unit 241 and the inverter 231 inverts data fed from the inverter 221 and outputs it as the display data D′00.
The data register 14 shown in FIG. 22 captures the display data D′00 to D′05, D′10 to D′15, and D′20 to D′25 fed from the data buffer 13 in synchronization with sampling pulses SP1 to SP176 as display data PD1 to PD528 and feeds them to the data latch 16. The control circuit 15 is made up of a plurality of inverters being connected in series. The control circuit 15 produces a strobe signal STB1 obtained by delaying the strobe signal STB fed from the control circuit 2 by predetermined period of time and a switching control signal SWA being in opposite phase with the strobe signal STB1. The control circuit 15 feeds the strobe signal STB1 to the data latch 16 and feeds the switching control signal SWA to the outputting circuit 19. The data latch 16, in synchronization with a rise of the strobe signal STB1 to be fed from the control circuit 15, captures the display data PD1 to PD528 fed from the data register 14 and holds, until the subsequent strobe signal STB1 is fed, that is, during one horizontal sync period, the captured display data PD1 to PD528. The gray scale voltage generating circuit 17, as shown in FIG. 24, is made up of resistors 251 to 2563 being cascade-connected Each of the resistors 251 to 2563 is so constructed that its resistance can meet an “applied voltage—transmittance characteristic” of the color LCD 1. In the gray scale voltage generating circuit 17, out of gray scale voltages VI1 to VI9, the gray scale voltage VI1 is applied to one terminal of the resistor 251, gray scale voltage VI2 is applied to a connection point between a resistor 257 and resistor 258, gray scale voltage VI3 is applied to a connection point between a resistor 2515 and a resistor 2516, and the gray scale voltage VI4 is applied to a connection point between a resistor 2523 to a resistor 2524. Moreover, in the gray scale voltage generating circuit 17, out of the gray scale voltages VI1 to VI9, the gray scale voltage VI5 is applied to a connection point between the resistor 2531 to 2532, gray scale voltage VI6 is applied to a connection point between a resistor 2539 to 2540, gray scale voltage VI5 is applied to a connection point between the resistor 2531 and resistor 2532, gray scale voltage VI6 is applied to a connection point between the resistor 2539 to the resistor 2540, and gray scale voltage VI7 is applied to a connection point between the resistor 2547 and resistor 2548, gray scale voltage VI8 is applied to a connection point between the resistor 2555 and resistor 2556, gray scale voltage VI9 is applied to one terminal of the resistor 2563. As a result, the gray scale voltage generating circuit 17 divides nine kinds of the gray scale voltages VI1 to VI9 based on a resistance ratio of the resistors 251 to 2563 and outputs 64 kinds of the gray scale voltages V1 to V64 whose polarity is inverted between a positive state and a negative state for every line relative to the common potential Vcom being applied to the common electrode of the color LCD 1.
The gray scale voltage selecting circuit 18 shown in FIG. 22 is made up of gray scale voltage selecting sections 181 to 18528. Each of the gray scale voltage selecting sections 181 to 18528, based on values of 6 bits of digital display data PD1 to PD528, selects one gray scale voltage out of 64 pieces of the gray scale voltages V1 to V64 to be fed from the gray scale voltage generating circuit 17 and feeds it to an amplifier corresponding to the outputting circuit 19. Since configurations of each of the gray scale voltage selecting sections 181 to 18528 are the same, only the configuration of the gray scale selecting section 181 is explained here. The gray scale voltage selecting section 181, as shown in FIG. 25, is made up of a multiplexer (MPX) 26, transfer gates 271 to 2764, and inverters 281 to 2864. The MPX 26, based on a value of corresponding 6 bits of the display data PD1, causes any one of 64 pieces of transfer gates 271 to 2764 to be turned ON. Each of the transfer gates 271 to 2764 is made up of a P-channel MOS transistor 29a and an N-channel MOS transistor 29b, which is turned ON by the MPX 26 and outputs a corresponding gray scale voltage as the data red signal, data green signal, or data blue signal. The outputting circuit 19 is made up of 528 pieces of outputting sections 191 to 19528 and each of the outputting sections 191 to 19528 has each of amplifiers 301 to 30528, and each of 528 pieces of switches 311 to 31528 placed on a latter stage of each of the amplifiers 301 to 30528. The outputting circuit 19 amplifies the corresponding data red signal, data green signal, and data blue signal fed from the gray scale voltage selecting circuit 18 and then applies them through switches 311 to 31528 which have been turned ON by a switching control signal SWA fed from the control circuit 15 to corresponding data electrode in the color LCD 1. In FIG. 25, the amplifier 301 placed to output a data red signal S1 corresponding to the display data PD1 and the switch 311 are shown.
Next, operations of the control circuit 2, gray scale power source 3, common power source 4, and data electrode driving circuit 5, out of operations of the driving circuit for the conventional color LCD 1, will be described by referring to a timing chart shown in FIG. 26. First, the control circuit 2 feeds a clock CLK (not shown), a strobe signal STB shown by (1) in FIG. 26, a horizontal start pulse STH being delayed by several pulses of the clock CLK behind the strobe signal STB shown by (2) in FIG. 26, and a polarity signal POL shown by (3) in FIG. 26, to a data electrode driving circuit 5. As a result, the shift register 12 in the data electrode driving circuit 5 performs shifting operations to shift the horizontal start pulse STH in synchronization with the clock CLK and outputs 176 bits of parallel sampling pulses SP1 to SP176. At almost the same time, the control circuit 2 converts each of the 6 bits of red data DR, green data DG, and blue data DB into 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25 and feeds the data to the data electrode driving circuit 5 (not shown). As a result, the 18 bits of the display data D00 to D05, D10 to D15, and D20 to D25, after being held during one pulse of the clock CLK1 by the data buffer 13 of the data electrode driving circuit 5 in synchronization with a clock CLK1 being delayed by a predetermined period of time behind the clock CLK, are fed to the data register 14 as display data D′00 to D′05, D′10 to D′15, and D′20 to D′25. Therefore, the display data D′00 to D′05, D′10 to D′15, and D′20 to D′25 are captured sequentially in synchronization with sampling pulses SP1 to SP176 fed from the shift register 12 in the data register 14 as display data PD1 to PD528 and then also captured simultaneously in the data latch 16 in synchronization with a rise of the strobe signal STB1 and is held during one horizontal period.
Next, in the gray scale power source 3 shown in FIG. 21, when the polarity signal POL shown by (3) in FIG. 26 is at a high level, switches 8a and 9a are turned ON and, at the same time, switches 8b and 9b are turned ON. This causes the supply voltage VDD to be applied to one terminal of the resistor 71 and one terminal of the resistor 710 to be connected to the ground and the gray scale voltages VI1 to VI9 (GND<V19<V18<V17<V16<V15<V14<V13<V12<V11<VDD) each having a positive polarity are produced (by (4) of FIG. 4, gray scale voltage VI1 is shown only). The gray scale voltages VI1 to VI9 of positive polarity, after having been amplified by the voltage followers 111 to 119, are fed to the gray scale voltage generating circuit 17 in the data driving circuit 5 shown in FIG. 22. Therefore, in the gray scale voltage generating circuit 17, the gray scale voltages VI1, to VI9 of positive polarity are divided based on resistance ratio of the resistors 251 to 2563 and, as a result, 64 pieces of the gray scale voltages V1 to V64 (the gray scale voltage V1 is the nearest to the supply voltage VDD and the gray scale voltage V64 is the nearest to the ground level) of the positive polarity are produced and then are fed to the gray scale voltage selecting circuit 18.
Therefore, in each of the gray scale voltage selecting sections 181 to 18528 in the gray scale voltage selecting circuit 18, the MPX 26 turns ON any one of the 64 pieces of the transfer gates 271 to 2764 based on values of the corresponding 6 bits of the display data PD1 to PD528. This causes the corresponding gray scale voltage to be output as the data red signal, data green signal, and data blue signal from the transfer gate 27 that have been turned ON. The data red signal, data green signal, and data blue signal are amplified by corresponding amplifiers 301 to 30528 in the outputting circuit 19. An output signal from each of the amplifiers 301 to 30528 is applied through switches 311 to 31528 having been turned ON by a switching control signal SWA (see (6) in FIG. 26) which rises with timing when the strobe signal STB shown by (1) in FIG. 26, as the data red signal, data green signal, and data blue signal S1 to S528, to corresponding data electrodes in the color LCD 1. A waveform of the data red signal S1 provided when a value of the display data PD1 is “000000” is shown by (7) in FIG. 26. In this case, in the gray scale voltage selecting section 181, the MPX 26, based on a value of the corresponding display data PD1 of “000000”, has the transfer gate 271 turned ON to cause the gray scale voltage V1 of the positive polarity to be output as the data red signal S1. Referring to (7) in FIG. 26, a reason why part of the data red signal S1 is shown by the dotted lines when the strobe signal STB is at a high level is that, since the switch 311 is turned OFF, the voltage to be applied in response to the data red signal S1 output from the outputting section 191 to the corresponding data electrode in the color LCD 1 is put into a stage of high impedance. On the other hand, the common power source 4, based on the high-level polarity signal POL, makes the common potential Vcom be at a ground level (see (5) in FIG. 26) and then feeds it to the common electrode in the color LCD 1. Therefore, a black color is displayed in a corresponding pixel in the color LCD 1 which is of normally white type.
Then, in the gray scale power source 3 shown in FIG. 21, when the polarity signal POL shown by (3) in FIG. 26 is at a high level, the switches 8a and 9a are turned OFF and the switches 8b and 9b are turned ON. This causes one terminal of the resistor 71 to be connected to the ground and the supply power VDD to be applied to one terminal of the resistor 710 and the gray scale voltages V11 to V19 of negative polarity (GND<V11<V12<V13<V14<V15<V16<V17<V18<V19<VDD) are generated (by (4) in FIG. 26, only the gray scale voltage V11 is shown). The gray scale voltages V11 to V19 of negative polarity, after having been amplified by the voltage followers 111 to 119, are fed to the gray scale voltage generating circuit 17 in the data driving circuit 5 shown in FIG. 22. Therefore, the gray scale voltages V11 to V19 of negative polarity are divided, based on the resistance ratio of the resistors 251 to 2563 and, as a result, 64 pieces of gray scale voltages V1 to V64 of negative polarity (gray scale voltage V1 is the nearest to a ground while the gray scale voltage V64 is nearest to the supply power VDD) are generated and are fed to the gray scale voltage selecting circuit 18. Therefore, in each of the gray scale voltage selecting sections 181 to 18528 in the gray scale voltage selecting circuit 18, the MPX 26, based on a value of the corresponding 6 bits of the display data PD1 to PD528, turns ON any one of the 64 pieces of the transfer gates 271 to 2764. This causes corresponding voltages to be generated from the transfer gate 27 having been turned ON as the data red signal, data green signal, and data blue signal. The data red signal, data green signal, and data blue signal are amplified by the corresponding amplifiers 301 to 30528 in the outputting circuit 19. Each of signals output from each of the amplifiers 301 to 30528 is applied, as the data red signal, data green signal, and data blue signal, to corresponding data electrode in the color LCD 1 through switches 311 to 31528 having been turned ON in response to the switching control signal SWA (refer to (6) in FIG. 26) which rises with timing when the strobe signal STB shown by (1) in FIG. 26 falls. One example of a waveform of the data red signal S1 appearing when a value of the display data PD1 is “000000” is shown by (7) in FIG. 26. In this case, in the gray scale voltage selecting section 181, the MPX 26, based on the value “000000” of the corresponding display data PD1, causes the transfer gate 271 to be turned ON and the gray scale voltage V1 of negative polarity to be output as the data red signal S1. On the other hand, the common power source 4, based on the low-level polarity signal POL, makes the common voltage be at a level of the supply voltage (VDD) and applies it to the common electrode in the color LCD 1. Therefore, a black color is displayed on a corresponding pixel in the normally-white type color LCD 1.
Thus, the method in which a data signal whose potential is inverted for every line relative to the common potential Vcom being applied to the common electrode in the color LCD 1 is fed to the data electrode and, at the same time, the common potential Vcom is inverted so as to be at the ground level and to be at a VDD level for every line is called a “line inverting driving method”. The line inverting driving method is conventionally used because continuous application of a voltage of a same polarity to a liquid crystal cell causes a life of the color LCD 1 to be shortened and, even if a voltage being applied to the liquid crystal cell is of opposite polarity, the liquid crystal cell has almost the same transmittance characteristic.
As described above, in the conventional driving circuit for the color LCD 1, each of the gray scale voltage selecting sections 181 to 18528 in the gray scale voltage selecting circuit 18 is made up of each of the transfer gates 271 to 2764. Therefore, the gray scale voltage selecting circuit 18 has 528×64 pieces of the transfer gates and a parasitic capacitance of about 500 pF as a whole. Also, as described above, in the conventional driving circuit for the color LCD 1, since the line inverting driving method is employed, in the gray scale power source 3 shown in FIG. 21, the gray scale voltage of positive polarity or of negative polarity are output by alternately changing over the switches 8a and 9a and switches 8b and 9b for every line. Moreover, as shown in FIG. 24, in the conventional driving circuit in the color LCD 1, the gray scale voltage generating circuit 17 is made up of resistors 251 to 2563 being cascade-connected to each other.
If a sum total of resistances of the resistors 251 to 2563 is “R”, after the switches 8a and 9a or switches 8b and 9b have been changed over, time T of at least 8×C×R (μsec) (99.97% of a final value) is required before the gray scale voltages V1 to V64 of positive or negative polarity being fed to the transfer gates 271 to 2764 making up each of the gray scale voltage selecting sections 181 to 18528 reaches a predetermined value. In the case of the color LCD 1 which provides 176×220 pixel resolution, the time T is about 50 μsec. Therefore, the sum total of the resistance values is 12.5 kΩ(=50×10−6/8/500×10−12). If the supply voltage VDD is 5 volts, since a current I flowing through the resistors 251 to 2563 being cascade-connected becomes 0.4 mA (=5/12.5×103), power consumption in the gray scale voltage generating circuit 17 is as high as 2 mW (=0.4×103×5). This power of 2 mW is consumed All the time in the gray scale voltage generating circuit 17. Moreover, as described above, the gray scale voltage selecting circuit 18 has a parasitic capacitance of about 500 pF. When the polarity of a voltage being applied to the resistors 251 to 2563 is changed for every line by the line inverting driving method, since a charging or discharging current flows through the parasitic capacitor C, the power consumption in the gray scale voltage selecting circuit 18 is 0.125 mW. The total power consumption of 2.125 mW is a value being not negligible in the portable electronic devices being driven by a battery or a like such as the notebook computer, palm-size computer, pocket computer, PDA, portable cellular phone, PHS or a like.
Moreover, as described above, since the parasitic capacitance C of the gray scale voltage selecting circuit 18 is as large as about 500 pF as a whole, it takes time charging or discharging the parasitic capacitor C at the time of the line inverting driving operation, which causes inferior contrast on the screen of the color LCD 1.
Furthermore, it is inevitably necessary to make small and lightweight the portable electronic devices being driven by the battery or the like such as the notebook computer, palm-size computer, pocket computer, PDA, portable cellular phone, PHS, or the like. However, in the conventional driving circuit for the color LCD 1, not only the gray scale power source 3 is placed separately outside of the data electrode driving circuit 5, but also the gray scale voltage selecting circuit 18 is made up of as many as 528×64 pieces of transfer gates. Therefore, the printed board requires an area sufficiently enough to house such the gray scale power source 3 and, as a result, the semiconductor integrated circuit (IC) making up the data electrode driving circuit 5 having such the gray scale voltage selecting circuit 18 naturally becomes large in size. This produces a bottle neck in scaling down and making lightweight the portable electronic devices.
Moreover, in the portable cellular phone or PHS, when the color LCD 1 providing 176×220 pixel resolution is driven at a frequency of about 60 Hz, one horizontal sync period is 60 to 70 μsec. On the other hand, an actual driving time of the color LCD 1 is about 40 μsec per one horizontal sync period. However, in the driving circuit of the color LCD 1, even during a period (about 20 to 30 μsec) not required for driving the color LCD 1, the amplifiers 301 to 30528 to drive the outputting circuit 19 are put in an active state and, therefore, power consumption is as large as about 24 mW. This produces a bottleneck in reducing power consumption in the above portable electronic devices.
Also, as described above, in the conventional driving circuit for the color LCD 1, assuming that, even if the polarity of the voltage being applied to a liquid crystal cell becomes opposite, the liquid crystal has a same transmittance characteristic, in the gray scale power voltage 3 shown in FIG. 21, the gray scale voltages VI1 to VI9 each having a same voltage are used, by inverting only the polarity. However, the applied voltage—transmittance characteristic in actual liquid cells differs between when a voltage of positive polarity is applied and when a voltage of negative polarity is applied, due to switching noises of the TFT serving as the switching element. Therefore, when the gray scale voltages VI1 to VI9 each having the same voltage but the opposite polarity are used, there is a problem in that color correction is difficult and an image of high quality cannot be obtained.
Inconveniences or shortcomings described above also occur even when the display screen of the color LCD 1 is comparatively small in size and a frame inverting driving method in which a data signal whose potential is inverted relative to common potentials being applied to the common electrode for every line and for every frame is fed to a data electrode, is employed. Moreover, the above inconveniences occur even in a driving circuit of a monochrome LCD in the same manner as described above.